As it is well known, one of the most delicate and complex operations in the functioning of flash memories is the electric erase of the same.
This erase operation comprises, in reality, more steps which, according to the technology and to the manufacturer of the flash memory, can be slightly different both in type and in number.
The selective verify steps of the flash memory cells are particularly problematic, such as the verify step of the deplete state, the so called depletion verify. This depletion verify step in fact requires, at least in some technologies, that high negative voltage values are applied to the gate terminals only of some cells of the memory, in particular, the cells which are deselected with respect to this depletion verify step. Only in this way it is possible to avoid leakage due to the undesired conduction by cells which, due to a higher erase speed, reach a negative threshold state, i.e., a deep depletion state at the end of an erase pulse, which, as it is known, interests a whole sector of a flash memory.
In other words, the application of the erase pulse to a sector of the flash memory, calibrated so as to ensure the erase of all the memory cells of the sector and thus regulated for the “harder” cells to be erased (cells with low erase speed) causes the switching, into a deep depletion state, of the “easier” cells to be erased (cells with high erase speed).
The depletion verify step thus needs a voltage with high negative value for carrying out a correct verification also of the cells having high erase speed.
From a circuit point of view, this implies the introduction, into a row decoder circuit, of suitable circuitry able to generate the high negative voltage required.
It is to be noted that this circuitry generating the high negative voltage inside the row decoder circuit is not necessary for the correct execution of the real erase step. In fact, in the erase step, a negative voltage value (normally equal to about −8V) is applied to the gate terminals of all the cells of a sector: the erase step of a flash memory is thus an operation which is non selective, but interests all the cells of a memory sector.
It is known to realize this circuitry generating the high negative voltage by introducing, into the row decoder circuit, suitable level shifters. These level shifters, even if realized in a distributed way, i.e., in such a way as to be shared by more rows of the memory matrix, often must however be integrated in the pitch of the cells and they thus increase the area occupation thereof. In the known solutions, these level shifters substantially double the area occupation of the row decoder circuit.
Row decoder circuits with very compact layout and able to apply a strongly negative voltage to all the cells of a memory sector are also known.
Such a circuit is schematically shown in FIG. 1, globally indicated with 1.
The row decoder circuit 1 comprises an input stage 2 connected to an output stage, in particular a row driver 3, in turn connected to a control or gate terminal G4 of the memory cells 4. The row decoder circuit 1 also comprises a decoupling stage 5, inserted between the input stage 2 and the row driver 3, as well as a biasing block 6, connected to the row driver 3.
More in particular, the input stage 2 is inserted between a first and a second supply voltage reference, in particular, a supply voltage Vdd and a ground GND and it has a first input terminal I21 connected to an address buffer Add, as well as a second input terminal I22 receiving a clock signal, Ck. The input stage 2 comprises a first transistor M1, a second transistor M2 and a third transistor M3, as well as selection transistors Mn (in the example, for sake of simplicity, only one has been shown) inserted, in series to each other, between the supply reference Vdd and the ground GND.
In the example shown in FIG. 1, the first transistor M1 is a PMOS transistor inserted between the supply voltage reference Vdd and an output terminal O2 of the input stage 2 and having a gate terminal connected to the gate terminal of the third transistor M3 and to the second input terminal I22 of the input stage 2. This third transistor M3 is of the NMOS type and it is inserted between the selection transistors Mn and the ground GND.
The second transistor M2 and the selection transistor Mn are transistors of the NMOS type, inserted between the output terminal O2 and the third transistor M3 and they have gate terminals connected to the first input terminal I21 of the input stage 2.
The signals applied to the input stage 2 can vary between the ground GND (0V) and the supply voltage Vdd, generally equal to 3V, as indicated on the bus Add.
The row driver 3 comprises a first transistor M4 and a second transistor M5 inserted, in series to each other, between a third supply voltage reference, in particular a regulation voltage Vreg, and a biasing node XB. The first transistor M4 and second transistor M5 have gate terminals connected to each other and to an input terminal I3 of the row driver 3, and they are interconnected in correspondence with an output terminal O3 of this row driver 3, in turn connected to a word line wl, i.e., a gate terminal G4 of the memory cells 4.
In particular, in the example shown in FIG. 1, the first transistor M4 is a PMOS transistor and the second transistor M5 is a NMOS transistor, interconnected in the form of a CMOS buffer.
The biasing node XB is also connected to the biasing block 6, in turn comprising a negative voltage generator G6 connected to this biasing node XB by means of a switch SW6. The switch SW6 is connected, in a fixed way, to the biasing node XB and, in an alternated or switched way, between the ground and the negative voltage generator G6. In substance, the switch SW6 allows to substitute the ground GND with the voltage supplied by the generator G6 for biasing the second transistor M5 of the row driver 3.
It is suitable to note that the signals applied to the row driver 3 can vary between the ground GND (0V) and a programming voltage value Vpcx, distinct from the supply voltage. Vdd and generally equal to 9V, as indicated in correspondence with the input terminal I3 of the row driver 3.
The decoupling stage 5 comprises a first transistor M6, inserted between the output terminal O2 of the input stage 2 and the input terminal I3 of the row driver 3 and having a gate terminal biased by means of a suitable signal P, as well as a second transistor M7, inserted between the regulation voltage reference Vreg and the input terminal I3 of the row driver 3 and having a gate terminal suitably driven by means of a signal Pull.
Also the signals applied to the decoupling stage 5 can vary between the ground GND (0V) and the programming voltage Vpcx (generally equal to 9V), as schematically indicated in correspondence with the first transistor M6.
The bulk terminals of the second transistor M2 and of the third transistor M3 of the input stage 2 as well as of the first transistor M6 of the decoupling stage 5 are connected to the ground GND.
The row decoder circuit 1 is used for applying a strongly negative voltage to the word lines of a memory sector during the erase step.
Unfortunately, the row decoder circuit 1 is not suitable for the application of sufficiently negative voltages in a selective way, for example to the word lines which are deselected during the depletion verify step, voltages which take into account the process variations due to the cells in the deep depletion state.
Also the row decoder circuit 1 shown in FIG. 1 must thus be integrated with suitable level shifters for correctly conducting the depletion verify step also on cells in a deep depletion state, with the consequent problems relative to the increase of the area occupation.